With that being said, we can conclude that setting the PLL_CLK as a clock source will help us choose the 480MHz PLL clock output as a clock source for the CPU (the CPU_CLK will be 480/2 MHz). The peripherals clock signals are APB_CLK, REF_TICK, LEDC_SCLK, APLL_CLK, and PLL_D2_CLK. The APB bus clock (APB_CLK) is derived from CPU_CLK, the division factor depends on the CPU_CLK source as shown in the table down below. The table down below from the datasheet shows the possible configurations for the clock. Note that this PLL clock is divided /2 or /4 before it’s fed to any CPU. The PLL_CLK is an internal PLL clock signal with a frequency of 320 MHz or 480 MHz. This results in a much higher frequency signal that’s derived from the main clock source (orders of magnitude in terms of frequency). The most important circuitry is the PLL (Phase-Locked Loop) which multiplies the input clock frequency (whether it’s an external crystal or internal oscillator). All embedded memory, external memory, and peripherals are located on the data bus and/or the instruction bus of these CPUs.īoth CPUs can be clocked from various sources internally or externally. Get The ESP32 Full Course Kit (List of components)Īs we’ve stated earlier in this series of tutorials, the ESP32 is a dual-core system with two Harvard Architecture Xtensa LX6 CPUs.Or just refer to the table for the exact components to be used in practical LABs for only this specific tutorial. You can either get the complete course kit for this series of tutorials using the link down below. Arduino IDE For ESP32 (Setup Guide) Hardware Components.Requirements For This Tutorial Prior Knowledge 7.1 ESP32 Low-Power CPU Clock Setting – Code Example.7 ESP32 Change CPU Speed (Frequency) – LAB.6.1 ESP32 Read Default Clocks – Code Example.3 Why Would You Need To Change ESP32 CPU Clock?.

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